The invention relates to an integrated circuit arrangement, that is to say a circuit arrangement which is arranged in a substrate, having at least one capacitor.
Such an integrated circuit arrangement is described in GB 2 294 591 A, for example. In order to produce the capacitor, first of all a layer made of amorphous silicon is deposited. A mask is produced above the latter, which mask comprises islands which are distributed on the layer made of amorphous silicon. The silicon is etched with the aid of the mask, so that the layer made of amorphous silicon obtains a roughened surface. The layer made of amorphous silicon is converted into a layer made of polysilicon by being heated, and serves as a first capacitor electrode of the capacitor. A capacitor dielectric is applied to the first capacitor electrode and a second capacitor electrode is applied to said dielectric.
The invention is based on the problem of specifying an integrated circuit arrangement having at least one capacitor which, in conjunction with a small space requirement and in comparison with the prior art, at the same time has a high capacitance. Furthermore, the intention is to specify a method for fabricating such an integrated circuit arrangement.
The problem is solved by means of an integrated circuit arrangement having at least one capacitor, in which the capacitor is arranged on a surface of a substrate. A first capacitor electrode of the capacitor has a lower part and a lateral part arranged on the lower part. The lateral part has a first lateral area and a second lateral area, which are opposite one another and whose distance from one another is smaller than a height of the lateral part. At least the first lateral area of the lateral part is undulatory, so that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate. The lateral part and also at least an upper area of the lower part which is remote from the surface of the substrate are provided with a capacitor dielectric. A second capacitor electrode adjoins the capacitor dielectric.
On account of the first lateral area of the first capacitor electrode, in comparison with a capacitor whose first capacitor electrode essentially has only horizontal areas, the capacitor has a higher capacitance with the same space requirement.
The bulges and the indentations enlarge the first lateral area comparison with a planar lateral area, so that the pacitance of the capacitor is increased without enlarging e space required by the capacitor.
The bulges and indentations are preferably undulatory, so that he first lateral area has no edges at which local electric field increases can form, and, consequently, the capacitor has particularly low leakage currents.
A method for fabricating such an integrated circuit arrangement is specified below, which method likewise solves the problem.
A layer sequence whose layers are composed alternately of a first material and a second material is produced on a surface of a substrate. A depression is produced which cuts through the layer sequence. The first material is subsequently subjected to wet etching selectively with respect to the second material down to a first depth. Conductive material is deposited, so that a lateral part of a first capacitor electrode of the capacitor is produced on a side wall of the depression, which lateral part has at least one undulatory lateral area which faces the depression and has bulges and indentations alternately. Parts of the conductive material which are arranged outside the depression are removed. The layer sequence is subsequently removed. The lateral part and a lower part of the first capacitor electrode are produced in such a way that the lateral part is arranged on the lower part. The lateral and at least an upper area of the lower part which is remote from the surface of the substrate are provided with a capacitor dielectric. A second capacitor electrode is produced in a manner adjoining the capacitor dielectric.
Through the wet etching of the first material selectively with respect to the second material, the side wall of the depression is altered in such a way that it is undulatory and has bulges and indentations alternately. This form is transferred to the lateral part of the first capacitor electrode by depositing the conductive material on the side wall of the depression.
The bulges and indentations run along lines each running in a plane parallel to the surface of the substrate since the layers likewise run parallel to the surface of the substrate. Each of the layers defines an indentation or a bulge, respectively.
The deeper the first material is etched by wet etching, the more pronounced are the bulges and the indentations.
By way of example, n-doped polysilicon is suitable as the first material, and undoped polysilicon is suitable as the second material. In this case, HNO3+HF, for example, is suitable as an etchant.
As an alternative, the first material may be composed of undoped polysilicon, while the second material is composed of p-doped polysilicon. In this case, choline, for example, is suitable as an etchant.
All materials which can be etched selectively with respect to one another are suitable as the first material and as the second material.
The use of polysilicon is particularly advantageous if the dopant concentration within the layers is varied gradually in the vertical direction. The consequence is that the same layer can be etched to different degrees. If the dopant concentration is set in such a way that the layers made of the first material can be etched less well in edge regions, that is to say in an upper and a lower region, then the indentations have a particularly soft profile in contrast to an edged profile.
A particularly high capacitance of the capacitor can be attained if the first capacitor electrode and/or the second capacitor electrode are composed of metal.
By way of example, the first capacitor electrode is composed of WN, platinum or ruthenium oxide. The second capacitor electrode is composed for example of TiN, tungsten or platinum.
A particularly high capacitance can be attained if the capacitor dielectric has a particularly high dielectric constant. Examples of suitable materials for the capacitor dielectric are Ta2O5, barium strontium titanate or aluminum oxide.
In order to simplify the process, it is advantageous if the lower part is produced at the same time as the lateral part. By way of example, the lower part is produced by depositing the conductive material during the production of the lateral part on the bottom of the depression. In this case, the first capacitor electrode comprises a single layer. A thickness of the lower part which is measured perpendicularly to the surface of the substrate essentially corresponds to a thickness of the lateral part which is equal to the distance between the two lateral areas. The lower part is disk-shaped. The lateral part is arranged along an edge of the lower part. Since the first lateral area faces the depression, the first lateral area points outward. The first capacitor electrode has the form of a cylinder open at the top. The first capacitor electrode is produced in the depression. In order to remove the parts of the conductive material which are arranged outside the depression, the depression may be filled with an auxiliary material. The auxiliary material serves as a mask during the etching of the conductive material, so that the conductive material is preserved in the depression.
As an alternative, the depression is produced around the first capacitor electrode to be produced. In this case, the lower part of the first capacitor electrode is produced under the layer sequence which is patterned by the depression. This can be done before the production or after the removal of the layer sequence. In this case, the first lateral area of the lateral part points inward.
By way of example, the layer sequence is produced on a conductive layer. During the production of the depression, the conductive layer is uncovered. The conductive material may subsequently be deposited. The conductive material outside the depression may be removed by being etched back, for example, so that the conductive layer is uncovered at the bottom of the depression. If the depression is intended to surround the first capacitor electrode, parts of the conductive layer which are arranged at the bottom of the depression are removed. If the first capacitor electrode is intended to be produced in the depression, the layer sequence is removed and then the parts of the conductive layer which are arranged under the layer sequence are removed. In both cases, the lower part of the first capacitor electrode is formed from the patterned conductive layer.
If the lateral part is produced after the lower part of the first capacitor electrode, then the lateral part may also be produced elsewhere than on the edge of the lower part. In particular, it is possible to produce a plurality of depressions per capacitor, so that the first capacitor electrode has a plurality of lateral parts. In order to obtain a particularly small space requirement for the capacitor, a mask can be used to produce the depressions, said mask being at least partly in spacer form, that is to say having small lateral dimensions.
A particularly high capacitance of the capacitor can be attained if the second lateral area of the lateral part also has indentations and bulges. To ensure that the form of the side wall of the depression is also transferred to the second lateral area during the deposition of the conductive material, the thicknesses of the layers of the layer sequence are greater than half the thickness of the deposited conductive material and/or the first depth down to which the first material is etched is less than half the thickness of the deposited conductive material.
As an alternative, only the first lateral area is undulatory.
The thicknesses of the layers are preferably between 10 and 30 nm. The thickness of the deposited conductive material, that is to say the distance between the two lateral areas of the lateral part of the first capacitor electrode, is preferably between 15 nm and 25 nm. The first material is preferably etched to a depth of between 10 nm and 30 nm.
The integrated circuit arrangement is a DRAM cell arrangement, for example.
By way of example, the lower part of the first capacitor electrode is connected to a transistor arranged underneath. At least the transistor and the capacitor form one of the memory cells. The memory cells are connected to word lines and bit lines running transversely with respect thereto.
By way of example, the DRAM cell arrangement is a one-transistor memory cell arrangement, in which each memory cell has a capacitor and a transistor connected thereto. In this case, the lower part of the first capacitor electrode is connected to a source/drain region of the transistor.
The connection is effected via a contact, for example. As an alternative, the lower part of the first capacitor electrode directly adjoins the source/drain region of the transistor.
An exemplary embodiment of the invention is explained in more detail below with reference to the figures.